The invention relates to a comparator circuit wherein a substantially rail-to-rail digital signal is generated indicating the higher of two analog voltages. Thus, the circuit is an analog to digital converter. The circuit displays a so-called indeterminate range in its response wherein linear signal response occurs. Since the comparator ordinarily has high gain, the indeterminate range is small so that for reasonable drive signals a truly digital output is available. The invention is applicable to complementary metal oxide semiconductor (CMOS) circuits. In CMOS, P- and N-channel insulated gate field effect transistor (IGFET) construction is employed to create monopolar devices. In the so-called P-well construction the P-channel devices are created in the N- type semiconductor substrate wafer. N-channel devices are fabricated into P-type wells that are separately created in the substrate. It has long since been realized that such a construction form produces bipolar transistors that are often regarded as parasitic. The P-well acts as the transistor base and is reverse biased with respect to the substrate which is returned to the most positive potential applied to the circuit. If an N-channel IGFET source or drain electrode in the P-well if forward biased an NPN transistor exists with its collector dedicated to the substrate. Such transistors can be useful as emitter followers and are often employed in combination with IGFETS to create CMOS circuits. However, in many circuits it is desirable to employ a non-dedicated collector type of the bipolar transistor. A way of doing so is disclosed in a patent application of Thomas M. Fredericksen, et al., Ser. No. 956,953, filed Nov. 2, 1978, and now abandoned in favor of a continuation application Ser. No. 304,701, filed Sept. 22, 1981. The teaching in that application, which is titled "A Lateral Transistor Useful in CMOS Integrated Circuits", is incorporated herein, by reference. That application shows that if a bipolar transistor emitter in a CMOS P-well is closely associated with a laterally spaced collector, a double collector transistor is produced with one collector dedicated to the substrate and the other collector available for external circuitry. It is shown that even with the dedicated collector, substantial and useful transistor action occurs at the lateral collector. I have discovered that when a pair of such transistors are connected differentially the resulting differential amplifier can have a suprisingly low offset voltage without trimming or any other special measures. This is particularly true when the lateral collectors are returned to the substrate by way of a pair of matched P-channel load IGFETs.
In the prior art, there are two well known ways of making a CMOS comparator circuit. In one approach a pair of N-channel transistors are connected differentially and their gates provide the comparator input terminals. A pair of matched P-channel transistors are connected as a differential to single ended load by connecting their gates together and to the drain of one of the transistors with the other drain comprising the single ended output. This single ended output can then drive an amplifier stage to provide the comparator output. Such circuits typically have offsets in the range of 7 to 30 millivolts. In the other prior-art approach a sampled data comparator is made up of a high gain capacitor-coupled amplifier. The input capacitor is alternately switched between the two comparator inputs by clocked switches and the amplifier is alternately forced to its switch point by another clocked switch. The amplifier output operates a latch or a clocked Flip Flop. The circuit has its offset eliminated by the switching action but such circuits are very complex and difficult to analyze. They require complicated clocking which adds to the circuit complexity.